Challenges & Advances of Mosfets Using High Mobility Material Channels Novel Quantum-corrected Semi-classical Ensemble Monte Carlo Simulator for Nano-scale Iii-v In0.47ga0.53as Tri-gate Finfets Electron Devices & Applications I

Complementary MOSFET (CMOS) using high mobility materials using III-V and Ge channels are expected to be one of promising devices for high performance and low power advanced LSIs in the future under sub-10 nm regime, because of the enhanced carrier conduction properties. The advantages of MOSFETs using those materials can basically originate in the low effective mass, which leads to high injection velocity and low scattering rate. However, suppression of short channel effects for applying to the short channel devices strongly demands ultrathin channels with the thickness of 10 nm or less. This requirement needs the deep understanding of carrier transport properties in the inversion layer in such nanostructures composed of the high mobility materials. In addition, since those devices employ MOS devices, the realization of defect-less MOS interfaces is strongly important. However, the understanding and control of MOS interface defects on the high mobility materials are still lacking. In this paper, we address technologies of forming MOS gate stacks, semiconductor channels and source/drain with emphasis on thin equivalent gate oxide, low MOS interface states and quantum well channels and low parasitic resistance. The physical mechanisms of determining current drive of III-V/Ge MOSFETs are discussed in terms of scattering mechanism and influence of MOS interface defects. The impacts of channel strain and the surface orientation on the electrical properties are also examined.